ROA-Brick Topology for Low-Skew Rotary Resonant Clock Network Design

Low Power Clock Network Design

Power is a primary concern in modern circuits. Clock distribution networks, in particular, are an essential element of a synchronous digital circuit and a significant power consumer. Clock distribution networks are subject to clock skew due to process, voltage, and temperature (PVT) variations and load imbalances. A target skew between sequentially-adjacent registers can be obtained in a balanc...

Low skew clock drivers and their system design considerations

Several varieties of clock drivers with 1ns or less skew from output-to-output are available from Motorola. Microprocessor-based systems are now running at 33MHz and beyond, and system clock distribution at these frequencies mandate the use of low skew clock drivers. Unfortunately, just plugging a high performance clock driver into a system does not guarantee trouble free operation. Only carefu...

Navigating Register Placement for Low Power Clock Network Design

In modern VLSI designs, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only in clock routing, we propose to navigate register placement to locations that enable further less clock routing wirelength. To minimize adverse i...

High Level Synthesis Methodology for Highly Testable and Nonzero Clock Skew Low Power Design

Design of Resonant Global Clock Distributions

This paper presents a new approach to global clock distribution in which traditional tree-driven grids are augmented with onchip inductors to resonate the clock capacitance at the fundamental frequency of the clock node. Rather than being dissipated as heat, the energy of the fundamental resonates between electric and magnetic forms. The clock drivers must only provide the energy necessary to o...